A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique
نویسندگان
چکیده
منابع مشابه
Design of Ultra Low power DET Flip-Flop with Power gating technique
1 PG scholar, M.E VLSI Design, Department of ECE, Info Institute of Engineering , Coimbatore. 2 Assistant Professor, Department of ECE, Info Institute of Engineering , Coimbatore. [email protected] _____________________________________________________________________________ _____ Abstract: The advancement of battery operated designs have abundantly increases the memory elements and reg...
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I Conclusion: In this Letter, we have shown that the method proposed in [2] could be used even in the case where non-neglectible values of feedback delay are encountered. A very interesting conclusion is that an optimal gain margin may be reached with a nonzero value, i.e. a physical delay value. Furthermore, this delay (higher than one sampling period) allows for dynamic element matching techn...
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ژورنال
عنوان ژورنال: Journal of Electrical and Computer Engineering
سال: 2014
ISSN: 2090-0147,2090-0155
DOI: 10.1155/2014/695832